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Old 03-13-2008, 10:21 AM   #41
freqmax
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Default Re: Questions about Minimig future

http://en.wikipedia.org/wiki/TMDS
"In the first stage each bit is either XOR or XNOR transformed against the previous bit, whilst the first bit is not transformed at all. The encoder chooses between XOR and XNOR by determining which will result in the fewest transitions; the ninth bit is added to show which was used. In the second stage, the first eight bits are optionally inverted to even out the balance of ones and zeros and therefore the sustained average DC level. The tenth bit is added to indicate whether this inversion took place."

bit0-7: Data
bit8: XOR or XNOR
bit9: Invert ..or not

I think bit8 might be a challenge to accomplish in a fast logic.

"The physical layer for TMDS is Current Mode Logic (CML), DC coupled and terminated to 3.3 Volts."

Essentially LVDS asfair. I think the docs said +/-100mV. So wikipedia is proberbly wrong at the volts level.
Xilinx Spartan-3/3E i/o mode LVDS25 should do it.
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Old 03-13-2008, 10:34 AM   #42
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Default Re: Questions about Minimig future


LVDS and CML 3.3v (DVI/HDMI) at the physical level don't look the same to me. But I stress I am not an analog person.
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Old 03-14-2008, 12:17 AM   #43
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Default Re: Questions about Minimig future

First one to try will find out :-D

Spartan-3A TMDS out-of-the-box is only available in non-handsoldering BGA packages.
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Old 03-14-2008, 01:26 AM   #44
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Default Re: Questions about Minimig future

Actually there is one TQFP part, but it's only 144 I/O (which is less than the current MiniMig) and not suitable.

Any future MiniMig board will have to use BGA chips.

I've got a BGA rework workstation and a flow solder oven ;-)

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Old 03-14-2008, 01:48 AM   #45
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Default Re: Questions about Minimig future

Quote:
LVDS and CML 3.3v (DVI/HDMI) at the physical level don't look the same to me.
As I said before the physical voltage levels are not that important. Its the difference in voltage between the complementary pair that decides if it is a logic 1 or 0.
However the voltages must remain in the common mode window of the receiver. LVDS normally terminated by 100 ohms generates at least 200mV differential at the receiver which is more than the 150mV receive window shown in the DVI spec.
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Old 03-14-2008, 03:28 AM   #46
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Default Re: Questions about Minimig future

@nBit7:
You think it should work?, if not what would be needed to make it work do you think?
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Old 03-14-2008, 04:34 AM   #47
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Default Re: Questions about Minimig future

Quote:
freqmax wrote:
@nBit7:
You think it should work?, if not what would be needed to make it work do you think?
I think that LVDS (current mode) drivers terminated to Vcc by 50 Ohms is a problem. If you have access to the termination then you should be able to get it working. Otherwise it may be possible to have a passive network that would allow it to work but it would likely have a drastic affect on max cable lengths. You would probably also need to have a floating (offset) GND reference on the LVDS side. I would have to do a more complete analysis of the LVDS drive circuitry to say anything with any level of assurance.
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Old 03-14-2008, 04:44 AM   #48
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Default Re: Questions about Minimig future

This App note suggests that it is possible (LVDS to CML) by using AC coupling. The protocol of DVI/HDMI should make AC coupling possible.

http://pdfserv.maxim-ic.com/en/an/hfan10v2.pdf
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Old 03-14-2008, 07:56 AM   #49
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Default Re: Questions about Minimig future

Quote:
nBit7 wrote:
This App note suggests that it is possible (LVDS to CML) by using AC coupling.
If I actually knew what that was I might be able to comment, I need to learn Analog. It's all "magic" AFAIC
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