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[billt]

Originally Posted by freqmax

mikej, As you seem to work with ASIC design. Do you think it's realisable to create a design consisting of a plain matrix of CLB elements? as way to an open source FPGA chip?

You mean to make our own FPGA silicon? That's an enormous amount of money. You don't necessarily need a lot of people, I've seen it done with 4 or 5 chip designers, 9 or 10 software guys to make the place/route tools etc. And you'd need some legal to make sense of existing patents to keep yourself out of trouble. But the EDA tools are HUGE expensive. The legal part is likely also HUGE expensive. And you'll also likely need a few years of work time for anything to happen. I'm not sure it's worth the trouble...

[freqmax]

Originally Posted by billt

You mean to make our own FPGA silicon? That's an enormous amount of money. You don't necessarily need a lot of people, I've seen it done with 4 or 5 chip designers, 9 or 10 software guys to make the place/route tools etc. And you'd need some legal to make sense of existing patents to keep yourself out of trouble. But the EDA tools are HUGE expensive. The legal part is likely also HUGE expensive. And you'll also likely need a few years of work time for anything to happen. I'm not sure it's worth the trouble...

The first FPGA was put on the market in 1985 so any patents for a plain matrix setup is likely obsolete many times over (5yrs). So for that part one can just make a simple circuit and duplicate it over and over. It won't be as good as the current topsellers but the point is to make a huge matrix available without the entanglements that currently exists.

As for software there already exist some really serious tries to replicate the existing routing software and that's with a unknown chip layout. Making the same effort for a simple and known layout should be way easier. Besides there are a lot of people prepared to write open source software..

A configurable logic matrix chip without ties to corporate directions and without ties to a specific platform would be of significant benefit in the long run.

[billt]

Originally Posted by freqmax

The first FPGA was put on the market in 1985 so any patents for a plain matrix setup is likely obsolete many times over (5yrs). So for that part one can just make a simple circuit and duplicate it over and over. It won't be as good as the current topsellers but the point is to make a huge matrix available without the entanglements that currently exists.

As for software there already exist some really serious tries to replicate the existing routing software and that's with a unknown chip layout. Making the same effort for a simple and known layout should be way easier. Besides there are a lot of people prepared to write open source software..

A configurable logic matrix chip without ties to corporate directions and without ties to a specific platform would be of significant benefit in the long run.

Getting anything designed will require a lot of money from someone. I can't imagine being completely free of corporate direction type issues, whatever you think those are. And I think there's enough FPGA and other chip patents to wade through and avoid that it would be a big effort to stay clean. And you could still get sued just for the giggles of it and have to pay for that fight, valid attack or not.

In the time it would take, we could be making interesting cores for existing FPGAs, I think that makes way more sense. I'd rather play with an FPGA Replay or other existing board, improving Minimig and adding new stuff, than spending 3+ years making a chip, debugging it, debugging software, and then start making fun cores and stuff.

I've done silicon layout of FPGA chips. Spent 8 or 9 years doing that in a small team. In that time was two technology generations based on an existing archtecture. I don't know how long it takes to define the architecture and code up RTL of that. I do know it takes a LOT of time just for layout implementation of whatever architecture, and I have an idea of how much the tools cost and how much masks cost, I know it takes a LLLLLLLOOOOOOOOOOOOTTTTTT of money from someone. Others are free to go at it, but I think the big money guys at Xilinx and Altera etc. are way better suited to making FPGA silicon. I can't imagine seeing such a project happen, just because of the money if nothing else.

I'd be interested to see if anyone ever does such a thing, but I expect I'd still prefer Xilinx/Altera big corp chips due to better performance and features.

[mikej]

I completely agree with Billt. Yes, I work designing super large ASICs.
The RTL coding for an FPGA is really easy, the layout is a bit more tricky but not difficult.

However, you have to pay a lot of money for the tools and cell library - the basic building blocks optimised for the fab and process you are using.

The mask set costs for any modern process are HUGE. Then you have to design the place and route software which is many many person years of work.

I can get a modern FPGA on a 28n process for a few $ in volume, because the big boys split the development cost between zillions of customers.

Both Xilinx and Altera provide decent free software, so I would rather spend my time using start of the art devices than designing them in this case

/Mike

[Ragoon]

As mikej says Altera & Xilinx makes good and affordable FPGA. There is no reason to compete with them.
But an ASIC for a stable version of the AGA core + cpu can be interesting to improve performances. For that you can use Hardcopy chip from Altera between fpga and asic. It's an FPGA without the memory layer and with fixed routes. So with your FPGA design you can have a fastest chip without redesigning it from scratch (just deal with some timing issues).

[freqmax]

I saw the thread about a dead CatWeasel and the problems to find the fault. As he has to make the right combination of attached hardware, interface hardware, drivers, configuration, and user software for it to work. Something missing = doesn't work, no explenation.

So it might be a good idea to create some test software for the board. Once the flashmemory with test software is inserted it would test the onboard MCU. If it works it could blink with a easy recognisable cycle. Then the MCU is used to test the FPGA. The FPGA is used to test the video ports, audio, keyboard, mouse, flashport stresstest for timing errors and so on..

That way it's easier to diagnose "bricked" boards without resorting to a heap of external test instruments. It could help with bad soldering diagnose too.

[Belial6]

Yeah, I wish we was wishing for that with my MiniMig when some modding when astray. I fixed what I broke, but I was really worried that I might have broken something else without noticing...

If that can be done for the RetroReplay, it would save a huge amount of effort in support.

[mikej]

yup, that's whats happening now - production test development.
Cheers,
Mike

[espskog]

Don't be shy to show screenshots and youtube clips from the board :-D

[alexh]

The only practical route would be a hardened FPGA but even then the NRE is pretty big.

[Fats]

Originally Posted by alexh

The only practical route would be a hardened FPGA but even then the NRE is pretty big.

There are alternatives: eASIC or ViASIC.

greets,
Staf.

[espskog]

Just out of curiosity: What would it take to redesign the OSD so that it resembles the early startup and has mouse support ? When the OSD menu gets lots of options, it might be cool to have a graphical menu system for configuring --- unless this eats up all the ARM memory ?

[Darrin]

Originally Posted by espskog

Just out of curiosity: What would it take to redesign the OSD so that it resembles the early startup and has mouse support ? When the OSD menu gets lots of options, it might be cool to have a graphical menu system for configuring --- unless this eats up all the ARM memory ?

Using the cursor keys to configure is fine by me. What I would like is a way to save several confurations:

Basic A500-like with KS1.3, OCS, 1 drive, etc @ 7MHz
Super Minimig with KS3.1, best chipset available, maximum RAM, hard file, etc
etc
etc

[Darrin]

Do we have any SysInfo results yet with a Minimig core?

[yaqube]

Originally Posted by Darrin

Do we have any SysInfo results yet with a Minimig core?

It was posted some time ago.



We are still working on it. Recently Tobias has implemented the missing bit field instructions and we are testing them now.

The performance will improve further when 32-bit wide transfers are implemented.