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[trekiej]

The tutorial in the book show ISE 6.1 software. During Compilation/Synthesis( probably not accurate ) the pins where set by software.
Is it possible to state how I want the pins to connect to my code? During schematic capture it seems to be possible.

I hope that came out right.

[mboehmer_e3b]

Is it possible to state how I want the pins to connect to my code? During schematic capture it seems to be possible.

You must supply a User Constraint File or use the GUI to define the pins.

An UCF is included as source file like any other VHDL file, and can carry things like

NET "BR" LOC = "P164";

In your top level VHDL file you can add the corresponding I/O structure on your own, like here:

OBUF_BR: OBUF
generic map(DRIVE => 8, IOSTANDARD => "LVTTL", SLEW => "SLOW")
port map(I => ZIII_BR, O => BR);

or you let the compiler do this job, and you will have to define I/O properties in addition inside the VHDL file.

The first solution gives you the possibility to define some parts of the I/O standard as generic statement (like maximum driving current, for example).

Michael

[RedskullDC]

Hi TrekieJ,

trekiej wrote:
The tutorial in the book show ISE 6.1 software. During Compilation/Synthesis( probably not accurate ) the pins where set by software.
Is it possible to state how I want the pins to connect to my code? During schematic capture it seems to be possible.
...

ISE6.1 is fairly antiquate now.
Suggest you update to the latest WebPack software from Xilinx.com
9.2 is quite stable, 10.1 is getting there...(imho).

Some really handy tools for creating UCF files (where you define pinouts etc.) for a variety of Xilinx based boards can be downloaded from the "PLD Oasis":
http://fafnir.rose-hulman.edu/~doering/PLD_Oasis/software.htm

You basically fill out the spreadsheet, then copy and paste straight to your UCF file.
Saves plenty of time

I've made some versions up for other boards, if the board you have isn't listed there, also added other constraints like drive strength,termination,slew rate.
Here is my Nexys2-1200 version for example:
http://au.geocities.com/redskulldc/UCF_Generator__Nexys2-12.xls


Hope this helps,
Red

[trekiej]

Thanks a lot to both of you.
I have a Xilinx X board with a Cool Runner II chip.
It has ISE9.1 if I remember correctly.
This will help me for sure.
Cheers.

[mboehmer_e3b]

I have a Xilinx X board with a Cool Runner II chip.
It has ISE9.1 if I remember correctly.

Which is - basically - a Philips CPLD family, but a nice one :-)

Hope you get your problem solved - the Xilinx software sometimes is a mess, especially in more complex projects there can be a spontaneous scrambling of the project file, which can cost you hours to recover (make snapshots when possible).

Take also care when upgrading - sometimes an upgrade triggers the scrambling...

Michael

[trekiej]

I will keep that in mind.
I will put 6.1 and I believe 7.1 on a Win98 machine.
The others will be on an XP,Vista machine.

Is there any time I will need the software to make pin connections for me? I bet power,clock,ground,and programming will be out of bounds. :-D

I searched Google and it was a bit helpful.
I can see why someone would want Open Source Software for CPLD,and FPGA.
PortablE looks to be a good programming language for FPGA's.