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[kamiga]

I've got an A500 with a VXL-30 accelerator, which is a 68030 with MMU.

If I make a small RAM board that interfaces to the address bus, data bus, and the memory control leads of '030, is there something more that needs to be done to tell the Amiga OS that additional memory is attached?

Is the auto-configuration process for detecting RAM at a particular location done just by checking whether memory is present, by reading and writing at the appropriate locations?

Or is there some proprietary protocol where the memory controller is expected to reply with key information?

While I would replace the existing DRAM controller, should I be seeing addresses in the range of $200000 - $9fffff, on the address bus? If there are multiple RAM controllers attached to the same bus, do the other controllers just be quiet when they see a request come in for an address out of the range they handle?

Does the auto-configuration process take care of adding the memory onto the free memory list?

Any pointers or references would help.

Thanks

Keith

[rkauer]

The 030 can address up to 1Gb RAM, but there are other limiter factors.

And is very hard to make a RAM controller. More information you can grab on "Lucas/Francis" projects (very old project, found in Amiga University).

To make a long answer short, no, you can't make a DIY RAM expansion for your accelerator.

[countzero]

I haven't checked the VXL-30, but if the RAM controller is on the accelerator (likely), and RAM board is only the board which holds the chips, you can do it (I mean it's still not easy, you have to figure out the pinout of the ram board interface somehow).

[meega]

rkauer wrote:
The 030 can address up to 1Gb RAM, but there are other limiter factors.

It's a 32-bit processor, with a 32-bit address range - that means up to 4GB. You certainly can't use all of that for RAM (in any computer) as other factors do indeed limit some things...

Dave Haynie wrote:
The A3000 implementation reserves 1.75 GigaBytes of address space for Zorro III expansion.

[kamiga]

rkauer wrote:

And is very hard to make a RAM controller. <snip>

To make a long answer short, no, you can't make a DIY RAM expansion for your accelerator.

Thanks for replying.

What are some of the limiting factors? What makes creating a RAM controller hard? There are a lot of new options for RAM and some of those "hard" problems disappear when you get rid of DRAM. Are you concerned about time, or what in particular?

I've also considered using the existing ram controller, and then tapping into the bus lines that feed the existing 16 chips. Find one larger chip, and then use the chip select line to each of the existing ones as an additional address qualifier to select the appropriate block of memory inside the new chip. Of course I'd need some glue logic to make that work, but it doesn't sound too hard.

I'm not very bright, but I do tend to stay with problems longer than most people.

Thanks

Keith

[kamiga]

countzero wrote:
I haven't checked the VXL-30, but if the RAM controller is on the accelerator (likely), and RAM board is only the board which holds the chips, you can do it (I mean it's still not easy, you have to figure out the pinout of the ram board interface somehow).

I'm almost certain that the existing DRAM controller is an FPGA by QuickLogic, and it's located ON THE RAM CARD.

http://www.amiga-hardware.com/downlo...xl30_4_big.jpg

Lower right hand corner. I'm pretty sure that's the controller.

Besides, I think that there are no other candidate chips on the main board. The main board has a spare-68000, the 68030, the FPU, and the pal chips. Nothing else with a butt-load of pins/wires AFAICT.


Yeah, figuring out the pinout will be one of the harder tasks for sure.

But there are two ways;

1: Do the controller and the ram
2: Intercept the pins going to ram, insert glue logic, and new ram (see other post)

The existing ram controller is only 68 pins, so most of the RAM chips are bussed together. Just thinking about, I think there would be two busses. 4-bits wide per ramchip, so 32-bits, 8 chip per bus. 16 chips total, so 2 busses.

Yeah I would have preferred the ram board JUST have the chips......

Thanks

Keith